Generally, in a scan design, the shifting of test data may result in excessive switching of the data stored in the flip-flops. Typically, in functional or system modes, there are generally only certain bursts of activity which only activate or load certain areas of a design. If a compression procedure is utilized, the data may be loaded all at once. This, however, may end up creating a lot of activity in the design, which may result in more power or voltage needed to load all of the data at once. This is generally more than what a chip may be designed for. In fact, loading of data all at once may end up creating up to a 50% average switching activity, at one time. For example, if every volume of information in the flip-flops that exists is changed, or is loaded, every other clock cycle, thus, there may be a constant power usage (e.g., 50% usage) at every cycle if the loads are alternated. This is too much power for a typical system. When there is a lot of power drawn (e.g., too much power), much more than a system was designed for, voltage droop may occur. For example, a significant voltage drop may be seen during each clock cycle.
In a typical power grid, which distributes power to different elements (e.g., different gates), a voltage drop (e.g., from an ideal voltage) may occur due to a significant amount of current being drawn based on every other data load (e.g., data switching). Since data is loaded in continuous bursts, data is always being loaded, and there is constantly a large power draw, which may result in the voltage droop. Additionally, responses are captured in flip-flops (e.g., scan chains) which may be shifted out to be observed (e.g., to observe them and determine whether a certain fault has manifested). Generally, there is limited or no control over these responses, which may result in a random mix of 0's and 1's being loaded or read, which are unnecessary bits, and which contribute to power usage. During functional operation there may be an average of 2-20% power usage (e.g., range). However, with continuous bursts, there may be up to a 50% power usage.
If there is a full scan design, artificial sequences of 0's and 1's may be generated to limit the number of transitions because there may be direct control with every single change. However, with various compression procedures, there generally are multiple don't care bits loaded. These compression procedures may leverage these don't care bits. However, there is limited or no control over these don't care bits, which may contain an arbitrary number of transitions. Don't care bits generally take the form of randomly assigned 0's and 1's, which may also increase switching and power usage.
Thus, it may be beneficial to provide an exemplary system, method, computer-accessible medium, and circuit for clock shifting in a scan design, which may overcome at least some of the deficiencies presented herein above.